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Taiwan Researchers Advance 2D Semiconductor Interface Engineering for Next-Generation AI Chips
分類:科研新訊| Research News
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發佈日期:2026-08-07
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Taiwan Researchers Advance 2D Semiconductor Interface Engineering for Next-Generation AI Chips

Research Published in Nature Electronics

 

Schematic illustration of the epitaxial interface engineering platform developed by the Taiwanese research team, overcoming a key bottleneck in two-dimensional semiconductors for future AI chip applications.

 

As demand for artificial intelligence (AI), large language models (LLMs), and high-performance computing (HPC) continues to grow, the semiconductor industry is facing increasing challenges in improving computing performance while reducing power consumption. With conventional silicon CMOS technology approaching its physical scaling limits at the 2-nanometer node and beyond, researchers worldwide are exploring new materials for the post-silicon era.

Among the most promising candidates are two-dimensional (2D) semiconductors, whose atomically thin structure offers the potential for lower power consumption, improved electrostatic control, and continued transistor scaling for future AI processors.

A research team led by Professor Wen-Hao Chang of National Yang Ming Chiao Tung University (NYCU), in collaboration with Dr. Iuliana Radu of Taiwan Semiconductor Manufacturing Co. (TSMC) and Professor Tsung-En Lee of NYCU, has developed a high-performance monolayer molybdenum disulfide (MoS₂) top-gate transistor by overcoming one of the most significant challenges in 2D semiconductor technology: interface engineering.

The research was supported by Taiwan’s National Science and Technology Council (NSTC) through the Å-Generation Advanced Semiconductor Program and the “Chip-based Industrial Innovation Program” Next-Generation Semiconductor Materials and Device Integration Program. The findings were published in the journal Nature Electronics.

 

Solving the Interface Challenge

Although 2D semiconductors have long been regarded as promising successors to silicon, integrating ultra-thin gate dielectric layers without degrading the material has remained a major obstacle.

Because monolayer materials are only one atom thick, conventional dielectric deposition often introduces defects and electron scattering, reducing carrier mobility and overall device performance.

Rather than introducing a new semiconductor material, the research team focused on improving the interface itself through an epitaxial interface engineering approach.

Using an ultra-high-vacuum process, the researchers deposited an ultrathin aluminum layer on monolayer MoS₂ before oxidizing it into an approximately 0.42-nanometer aluminum oxide interfacial layer. The atomically smooth interface significantly reduced electron scattering while preserving both ultra-thin dimensions and excellent electrical performance.

The resulting transistors demonstrated world-leading transconductance together with extremely low leakage current and stable device operation, representing a significant step toward practical applications of 2D semiconductor devices.

 

Implications for Future AI Chips

Although the research remains at the device level, it addresses several key requirements for next-generation AI processors.

Higher transconductance enables faster transistor switching, while lower leakage current reduces standby power consumption. Improved interface quality also enhances long-term device reliability—critical factors for AI accelerators operating in large-scale data centers, edge AI systems, and high-performance computing platforms.

If successfully integrated into future semiconductor manufacturing processes, the technology could contribute to next-generation AI GPUs, AI ASICs, edge AI processors, mobile AI system-on-chip (SoC) devices, neuromorphic computing hardware, and ultra-low-power AI sensors.

 

Toward the Post-Silicon Era

As AI semiconductor development increasingly extends beyond conventional silicon scaling, the industry is investing in a broad range of enabling technologies, including advanced process nodes, chiplet architectures, advanced packaging, high-bandwidth memory (HBM), optical interconnects, and emerging semiconductor materials.

The Taiwan team’s achievement represents more than an improvement in transistor performance. By establishing a scalable epitaxial interface engineering platform applicable to a wide range of 2D semiconductor materials, the research provides a potential pathway toward future post-silicon AI electronics while reinforcing Taiwan’s position in next-generation semiconductor innovation.

Journal: Nature Electronics

Paper Title: High-transconductance molybdenum disulfide top-gate transistors using epitaxial interface engineering

Research Card

Field

Content

Research Title

Epitaxial Interface Engineering Advances 2D Semiconductors for Next-Generation AI Chips

One-sentence Summary

Researchers developed a high-performance monolayer MoS₂ top-gate transistor using epitaxial interface engineering, paving the way for low-power post-silicon electronics and future AI processors.

Keywords

2D Semiconductors、MoS₂、Interface Engineering、AI Chips、Post-Silicon Electronics

Research Area

Semiconductor Devices and Electronic Engineering

Applications

AI Processors、Edge AI、AI ASICs、Neuromorphic Computing、Low-Power Electronics

Funding

NSTC Taiwan

Institution

National Yang Ming Chiao Tung University, Taiwan Semiconductor Manufacturing Co.